The rate at which data are transmitted through communication networks has dramatically increased in recent years. Fueled by progresses achieved in fiber and optoelectronic devices and techniques such as DWDM (Dense Wavelength Division Multiplexing), which allows multiplying the bandwidth of a single fiber by merging many wavelengths on it. Telecommunications and networking industry had to develop devices capable of routing and switching the resulting huge amount of data that converges, to be dispatched, at each network node. Typically, routers and switches situated at those network nodes have now to cope with the requirement of having to move data at aggregate rates that must be expressed in hundredths of giga (109) bits per second while multi tera (1012) bits per second rates must be considered for the new devices under development.
If considerable progress have been made in optoelectronic, allowing this level of performances in the transport of data from node to node, it remains that switching and routing of the data is still done in the electrical domain at each network node. This, essentially, because there is no optical memory available yet that would permits storing temporarily the frames of transmitted data while they are examined to determine their final destination. This must still be done in the electrical domain using the traditional semiconductor technologies and memories.
Improvements in semiconductor processes are making possible integrated circuits of increasing size and complexity. As a consequence, since the clock rates reach very high frequency, signals carrying data must be of high quality to detect logic levels. A standard solution for analyzing the quality of received signals consists in visualizing the eye diagram of measurement of a transmitted train of signals. By the level of opening in the diagram it becomes easy to appreciate the quality of the transmitted information, as illustrated on FIGS. 1a and 1b. The more the “eye” closes, the more difficult is the capability to understand if the switching transition has taken place or if the shift of the signal baseline is due to background noise. However, due to the clock rate, oscilloscopes require for such measurements are very expansive and, thus, are generally not used in real environment to test system efficiency but only in development laboratories. Moreover, the receiver must be removed during such measurements to avoid signal perturbations.
Another solution consists in over-sampling the high-speed received signal and accumulating results so as to determine where transitions take places. High-speed signal receivers are often based upon an over-sampling mechanism used to analyze signal transitions so as to determine the signal clock and thus, the best bit sampling position. This mechanism may be used to analyze the quality of the high-speed received signal. FIGS. 2 and 3 illustrate such solution. As shown on FIG. 2, a signal having a period P1 may be sampled by a system based on a clock having a period P2 smaller than P1, in this example, P2=P1/30. Sampled points are memorized in a register, for example a 40 bit register. FIG. 3 represents an example illustrating this known method. At time i, a first set of sampled points 300-1 is memorized in the above mentioned 40 bit register and an XOR operation is performed between these sampled points and the sames, shifted of 1 bit to the right, referred to as 305-1, to obtain result 310-1 characterizing the signal transition location. Result 310-1 is memorized in a 39 bit register. Signal transitions took place where a bit equal to 1 has been found. Then, at time i+1, a new set of sampled points 300-2 is memorized in the same 40 bit register and the XOR operation is performed between these sampled points and the sames, shifted of 1 bit to the right, referred to as 305-2, to obtain result 310-2. An OR operation is performed on this result 310-2 and the value stored in the 39 bit register. The OR result is stored in the 39 bit register, replacing the previous result. Then, the process is repeated at time i+2, and so on. At the end of the process, the value 315 stored in the 39 bit register characterizes the quality of the high-speed received signal by showing all the positions wherein the signal transitions took places. This value may be transformed so as to be easier to analyze. Such a transformation may consist, for example, in replacing the 0 by “−” and the 1 by “×” as illustrated by reference 320. In the following description, this representation is referred to as a digital eye. Thus, the ratio of the number L2 of “−” with the number L1 of “×” characterizes the quality of the high-speed received signal. It is to be noticed that the process must run during a sufficient period to analyze an important number of signal transitions.
To use efficiently this method, the clock rate of the signal must be a multiple of the clock rate of the sampling system and the ratio of these clock rates must be large enough. As a consequence, it can not be used to analyze system wherein the clock rate is such that it is not possible to sample points with an adequate clock rate due to technology limits. For example, considering a data communication link running at 2.5 Gbps, sampling 30 values per clock period means that a value must be sampled each 13.3 ps. Such sampling rate may not be reached at reasonable cost when considering the required accuracy of clock shift and the latch power consumption.
There is thus a need for a method and systems adapted to analyze the quality of high-speed signal when the clock rate of the sampling system does not allow to over-sample the signal.